1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to closely spaced gate electrode structures having full nitride encapsulation.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features have been steadily decreasing in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. However, commensurate with the on-going shrinkage of feature sizes, certain size-related problems arise that may at least partially offset the advantages that may be obtained by simple size reduction alone. Generally speaking, decreasing the size of, for instance, circuit elements such as MOS transistors and the like, may lead to superior performance characteristics due to a decreased channel length of the transistor element, thereby resulting in higher drive current capabilities and enhanced switching speeds. Upon decreasing channel length, however, the pitch between adjacent transistors likewise decreases, thereby limiting the size of the conductive contact elements—e.g., those elements that provide electrical connection to the transistor, such as contact vias and the like—that may fit within the available real estate. Accordingly, the electrical resistance of conductive contact elements becomes a significant issue in the overall transistor design, since the cross-sectional area of these elements is similarly decreased. Moreover, the cross-sectional area of the contact vias, together with the characteristics of the materials they comprise, may have a significant influence on the effective electrical resistance and overall performance of these circuit elements.
As integrated circuits become smaller and more closely spaced—i.e., as the number of circuit elements that are packed within a given unit area of a semiconductor device substrate increases—the greater the number of interconnections that are required between these circuit elements. Furthermore, it is not uncommon for the number of required interconnects to increase in a non-linear fashion relative to the number of circuit elements, such that the amount of real estate available for interconnects becomes even further limited, thus increasing the likelihood that the cross-sectional area of critical conductive elements might be further reduced.
Presently, integration schemes used for manufacturing transistor elements based on the current design technology node (e.g., 32/28 nm) permit the use of photolithography processes which can readily achieve a resist patterning that allows the formation of adequately sized contact elements—i.e., contact elements having acceptable electrical resistance characteristics—while still maintaining a robust minimum spacing between the contact elements and adjacent gate electrodes. With respect to FIGS. 1a-1b, one illustrative embodiment of a prior art semiconductor device utilizing such a contact element configuration will now be described.
FIG. 1a schematically shows a cross-sectional view of an illustrative semiconductor device 100 comprising a substrate 101, in and above which transistor elements 150a and 150b may be formed with a gate pitch 152P. As is well known in the art, gate pitch 152P is generally understood to be the lateral distance measured from the left-most sidewall of the gate electrode material 106 of the transistor element 150a to the left-most sidewall of the gate electrode material 106 of the transistor element 150b The substrate 101 may represent any appropriate substrate on which may be formed a semiconductor layer 102, such as a silicon-based layer, or any other appropriate semiconductor material that facilitates the formation of the transistor elements 150a, 150b. It should be appreciated that the semiconductor layer 102, even if provided as a silicon-based layer, may include other materials, such as germanium, carbon and the like, in addition to an appropriate dopant species for establishing the requisite conductivity type in an active region (not shown) of the semiconductor layer 102. Furthermore, in some illustrative embodiments, transistor elements 150a, 150b may be formed as bulk transistors, i.e., the semiconductor layer 102 may be formed on or be part of a substantially crystalline substrate material, while in other cases specific device regions of the device 100 or the entire device 100 may be formed on the basis of a silicon-on-insulator (SOI) architecture, in which a buried insulating layer (not shown) may be provided below the semiconductor layer 102.
As shown in FIG. 1a, each of the transistor elements 150a, 150b may comprise a gate electrode structure 110 having a gate length 151L and a lateral space 153S between adjacent gates. Gate electrode structure 110 may include, for instance, a gate dielectric material 107, such as a silicon dioxide based gate dielectric and the like, above which may be formed a gate electrode material 106, such as a polysilicon material and the like. Highly doped source and drain regions 104, including extension regions 105 that usually comprise a dopant concentration less than the highly doped regions 104, may also be formed in an active region of the semiconductor layer 102. The source and drain regions 104, including the extension regions 105, are laterally separated by a channel region 103, which is electrically and physically isolated from the gate electrode material 106 by the gate dielectric material 107.
Sidewall spacer structures 111 having an overall thickness 154T may also be provided on the sidewalls of the gate electrode structures 110. Depending on the process strategy, the sidewall spacer structures 111 may include two or even more spacer elements, such as offset spacers, conformal liners, and the like. FIG. 1a depicts one illustrative embodiment, wherein the sidewall spacer structures 111 each comprise an offset spacer 111a, conformal liner or spacer 111b, and a spacer element 111c. Furthermore, the gate electrode structures 110 may also comprise a metal silicide contact region 112 to facilitate electrical connectivity, and similar metal silicide contact regions 113 may be formed in the drain and source regions of the transistor elements 150a, 150b. 
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of well-established process techniques. For instance, the gate electrode structures 110 may be formed on the basis of sophisticated deposition and/or oxidation techniques for forming the gate dielectric material 107, wherein an appropriate thickness and material type, such as silicon dioxide, may be selected depending on device requirements. Thereafter, sophisticated lithography and etch techniques may be used for forming the gate electrode material 106, which, in some illustrative may comprise polysilicon and the like.
Next, the sidewall spacer structures 111 may be formed, at least partially, so as to act as an appropriate implantation mask for creating the lateral dopant profile for the drain and source regions 104 and extension regions 105. Offset spacers 111a, if required, may be comprised of any appropriate dielectric material, such as silicon dioxide, and may be formed as follows. In some illustrative embodiments, the dielectric material layer may be conformally deposited over the semiconductor device 100 by an appropriate deposition process, such as low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). In other illustrative embodiments, the dielectric material layer may be formed by exposing the surfaces of the semiconductor device 100 to an appropriate oxidizing ambient. Thereafter, the dielectric material layer may be anisotropically etched to remove horizontal portions of the layer so as to form the offset spacers 111a. 
Further, the sidewall spacer structure 111 may comprise a conformal liner or spacer 111b, which may be formed to exhibit a substantially L-shaped configuration. That is, the conformal spacer 111b may comprise a portion of a specified thickness that extends along the sidewall of the gate electrode 106 and may also comprise a portion having substantially the same thickness that extends along a part of the semiconductor layer 102, in which the source/drain and extension regions 104, 105 are to be formed. Consequently, the conformal spacer 111b may have a shape which substantially corresponds to the shape of the gate electrode 106, with a “horizontal” portion extending along a part of the drain and source regions 104, thereby separating one or more additional spacer elements 111c from the gate electrode 106 and the source/drain and extension regions 104, 105.
As shown in FIG. 1a, the sidewall spacer structure 111 may further comprise a sidewall spacer element 111c which may be formed using well known techniques. For example, in some illustrative embodiments, sidewall spacer element 111c may be formed of a dielectric material that may exhibit a significant etch selectivity with respect to the dielectric material of the conformal spacer 111b in view of a specific etch recipe so as to enable a selective removal of the spacer element 111c while substantially maintaining the conformal spacer 111b. For example, in one illustrative embodiment, the conformal or L-shaped spacer 111b may be comprised of silicon dioxide, while spacer element 111c may be comprised of silicon nitride. However, other regimes for the spacers 111b and 111c may be contemplated. For instance, in another illustrative embodiment, the L-shaped spacer 111b may be comprised of silicon nitride, while the spacer element 111c may be formed of silicon dioxide.
Prior to the deposition and/or removal of respective portions of the sidewall spacer structure 111, various implantation processes may be performed in order to obtain the required lateral dopant profile in the extension regions 105, and in the source/drain regions 104. It should be appreciated that a plurality of implantation processes may be required, such as pre-amorphization implantation, halo implantation, extension implantation and deep drain and source implantations for obtaining the required complex dopant profile. Furthermore, during the formation of the transistor structures 150a, 150b as shown, one or more high temperature treatments may be required, for instance, for activating dopants and re-crystallizing implantation-induced damage and the like. Finally, the metal silicide regions 112 and 113 may be formed in a common process based on well-known deposition, annealing, and etching techniques.
FIG. 1b shows the semiconductor device 100 of FIG. 1a in a further advanced stage of manufacturing. As shown in FIG. 1b, a contact etch stop layer 114 may be formed above transistor elements 150a, 150b so as to facilitate formation of a contact via 119 using techniques that are well known in the art, and as will be discussed in detail below. Thereafter, an interlayer dielectric material 116 of a first metallization layer may be deposited above the semiconductor device 100. Etch stop layer 114 may, in some illustrative embodiments, comprise a material that provides a suitable etch selectivity with respect to the interlayer dielectric material 116. For example, the interlayer dielectric material 116 may, in some embodiments, comprise a silicon dioxide material, and may be formed using a non-conformal deposition process such as a spin-on glass (SOG) technique, and the like. In such embodiments, a suitable etch selectivity may be obtained with an etch stop layer 114 comprised of silicon nitride or silicon oxynitride material.
In some illustrative embodiments, a material layer having a specified intrinsic stress may be formed above the semiconductor device 100 so as to thereby enhance the performance of one or both of the transistor elements 150a, 150b. The intrinsic stress may either be a compressive stress or a tensile stress, depending on the specified device characteristics and process requirements. In one embodiment, etch stop layer 114 may comprise the specified intrinsic stress, whereas in other embodiments an additional dielectric material layer 115 comprising the specified intrinsic stress may be deposited above etch stop layer 114 prior to forming interlayer dielectric material 116.
As further illustrated in FIG. 1b, an etch mask 117, such as a photoresist mask, may then be formed above interlayer dielectric material 116. The etch mask 117 may subsequently be patterned, using appropriate photolithography techniques, so as to define an opening 118 corresponding to the contact via opening 119 that is to be formed in the interlayer dielectric material 116. Thereafter, the contact via opening 119 may be formed based on an appropriately designed anisotropic etch process 120, such as a reactive ion etch (RIE) process and the like, recipes for which are well known in the art.
Based on the current design technology node, one illustrative embodiment of the semiconductor device 100 utilizes a nominal gate length 151L of approximately 32 nm, which in some instances may result an actual gate length in the range of 35-40 nm. With a nominal gate length 151L of 32 nm, the gate pitch 152P may in some cases be on the order 130 nm, thereby leaving a lateral space 153S between adjacent gates of approximately 90 nm. Moreover, in some process strategies, wherein the overall thickness 154T of the sidewall spacer structures 111 may range from 10-30 nm, the remaining lateral space 155S available between adjacent gate electrode structures 110 (including sidewall spacer structures 111) may be reduced to approximately 40-60 nm. Nonetheless, 40-60 nm leaves an acceptable amount of space for using available photolithography techniques to form an adequately-sized contact via opening 119 having a width in the range of 25-40 nm, which is more than sufficient to prevent the electrical resistance of the contact element from becoming unduly high.
However, it should be noted that, as the nominal size of design technology nodes decreases, it becomes increasingly difficult to utilize available photolithography techniques and still achieve a robust minimum spacing between a contact element and adjacent gate electrode structures without significantly reducing the real estate available for forming the actual contact element. For example, aggressively sized transistor elements based on a 20 nm design technology node may have a nominal gate length of 26 nm, resulting in an actual gate length that is on the order of 28-30 nm. Furthermore, the gate pitch 154P may be reduced to approximately 80 nm. When implementing a process strategy that requires a total gate sidewall spacer thickness of as little as 10-16 nm, the remaining lateral space 155S between adjacent gate electrode structures may be reduced to as low as approximately 25 nm. Based on available photolithography techniques, such a small available space may lead to contact element widths in the range of 10-15 nm, thereby resulting in unacceptably high contact element resistance levels.
Accordingly, there is a need to implement new design strategies to address both the manufacturing and performance issues associated with integration schemes for aggressively sized transistor elements. The present disclosure relates to methods and devices for avoiding or at least reducing the effects of one or more of the problems identified above.